1. Field of the Invention
This invention relates to a dynamic addressing display device and a dynamic addressing display system using the devices.
2. Description of Related Art
Generally, a dynamic addressing system which drives a liquid crystal display panel in a time division manner is used for a large-capacity liquid crystal display (LCD). In this addressing system, the display panel contains scan electrodes and data electrodes which are disposed like a matrix; a voltage is applied in sequence to the scan electrodes in a time division manner for scanning the scan electrodes and in synchronization with the scanning, a voltage is selectively applied to the data electrodes in response to the display contents at the time. This system displays the picture elements formed at the intersections of the scan electrodes and data electrodes as desired.
Recently, integration of drive circuits in a dynamic addressing LCD device has been advanced to one semiconductor chip on which a large number of drive circuits are mounted, and the numbers of drive circuits have been standardized for a decreased cost. However, the standardized numbers of drive circuits often mismatch the display capacity determined by market's needs because the specifications required for LCD devices vary from one application to another.
FIG. 1 shows an example of an LCD device where the number of output circuits of a data electrode driver does not match the number of picture elements or dots per row required to display one character on a display panel. The device shown in FIG. 1 comprises a display panel 13 containing scan electrodes (not shown) and data electrodes (not shown) which are disposed like a matrix, a scanning driver block 10 for driving the scan electrodes and a data driver block 6 for driving the data electrodes. The number of picture elements or dots required to display one character on the display panel 13 is 24.times.24 (length.times.breadth), while a data driver 9 in the data driver block 6 has 32 output circuits, the number of which is greater by eight than the number of picture elements per row required to display one character on the panel 13. A scanning driver 12 in the scanning driver block 10 has 24 output circuits, the number of which matches the number of picture elements per row required to display one character on the panel 13.
The scanning driver block 10 comprises a shift register 11 and a driver 12. A scanning data signal and a scanning clock signal are fed through lines 4 and 5 respectively into the shift register 11. When the clock signal is fed into the shift register 11, the scanning data stored in the shift register 11 is sent to the driver 12 in parallel through 24 output circuits 11a. The driver 12 is responsive to the received scanning data for applying voltage in parallel through 24 output circuits 12a to turn on, for example, the first scan electrode. When a new clock signal is fed into the shift register 11, the scanning data signal in the shift register 11 is shifted one step and the scanning data at the time is sent to the driver 12 in parallel. In response to the received scanning data, the driver 12 turns on, for example, the second scan electrode.
Likewise, when 24 clock signals equal to the number of the scan electrodes are fed into the shift register 11, 24 scan electrodes are turned on in sequence and one scan terminates. This operation sequence is repeated on a predetermined cycle for scanning the scan electrodes.
The data driver block 6 comprises a shift register 7, a latch 8 and a driver 9. A data clock signal and a dot data signal are sent to the shift register 7 through lines 1 and 3 respectively. A latch signal is sent to the latch 8 through a line 2.
In response to the data clock signals, desired dot data is sent to the shift register 7 in sequence for storage. When as many dot data pieces as 32 dots of the display panel 13 have been sent to the shift register 7, the dot data pieces are sent to the latch 8 in parallel through output circuits 7a and 7b in synchronization with the above-mentioned scanning by the latch signal. When the dot data pieces are sent to the latch 8, dot data on a new cycle is sent to the shift register 7 for storage.
When the dot data pieces are sent to the latch 8, immediately they are sent out from the latch 8 to the driver 9 in parallel through output circuits 8a and 8b. When receiving the dot data pieces, the driver 9 sends them to the data electrodes in parallel through output circuits 9a and 9b to drive the data electrodes, so that information on the cycle is displayed on the display panel 13. This operation sequence is repeated to display desired information on the display panel 13.
Although the necessary numbers of the dot data signals and the data clock signals for the LCD device are each 24 which equals the number of the data electrodes of the display panel 13, 32 dot data signals and 32 data clock signals are generated and sent to the shift register 7 because the data driver 9 in the data driver block 6 contains 32 output circuits. At the time, eight of the dot data signals are also sent to the driver 9 through eight output circuits 7b and the eight output circuits 8b, but are not used for operation of the display panel 13 because eight output circuits 9b are not connected to the data electrodes.
With the LCD device described above, the number of the output circuits of the data driver is greater than the number of the picture elements or dots per row required to display one character on the display panel, or the number of data electrodes, thus dot data signals and data clock signals for the extra data driver bits also needs to be generated.
Further, for example, to build a large-capacity LCD system for public display of a big screen, a display system must be made up of display units of size that can be manufactured for cascading them to provide the desired big screen from restrictions of outer dimensions of the units that can be manufactured. In this case, unified control of the drive circuits of the display units as one drive system is preferable to separate control of the units because the circuit configuration for the former is often simplified.
However, to use the display device shown in FIG. 1 as the display unit, extra operation of generating the dot data signals and data clock signals for the extra data driver bits is involved as described above, and if such signals cannot be generated, control circuits of different configurations must be provided for each display unit to control the drive circuits of the display units separately, thus the circuit configuration becomes complicated.